1. Field of the Invention
The present invention generally relates to an image sensor, and more particularly to the readout architecture for an image sensor with horizontal binning function.
2. Description of the Prior Art
Semiconductor based image sensors, such as charge-coupled devices (CCDs) or complementary metal-oxide-semiconductor (CMOS) sensors, are widely used, for example, in cameras or camcorders, to convert images of visible light into electronic signals that can then be stored, transmitted or displayed.
For an image sensor, such as state-of-the-art CMOS image sensor, a column amplifier (CA) is used to correspondingly read out image signals in each column (or bit line). One of the reasons to provide a gain at this early stage of an analog chain is to acquire a better signal-to-noise ratio (SNR). FIG. 1 shows the conventional readout architecture for an image sensor, in which each column (col1, col2, etc.) is correspondingly connected to an associated column amplifier (CA1, CA2, etc.). The signals are then sent, in sequence, to a following programmable gain amplifier (PGA) via a switch network. Specifically, the sample-and-hold reset (SHR) levels in the capacitors (CSHRn, n=1, 2, . . . ) of each column are controllably sent in sequence to the PGA, and the sample-and-hold (image) signals (SHS) in the capacitors (CSHSn, n=1, 2, . . . ) of each column are controllably sent in sequence to the PGA.
As more pixels (or photodiodes) are manufactured in an image sensor, the area, and thus the associated intensity, of each pixel become smaller. Accordingly, the signals from two or more pixels are sometimes added up (commonly called “binning”) to enhance the intensity so as to achieve better SNR. FIG. 2 shows the conventional readout architecture for an image sensor with binning function, in which each column (col1, col2, etc.) is correspondingly connected to an associated column amplifier (CA1, CA2, etc.). Before the signals are sent to the following PGA, the signals of a desired number of binning columns are added up (or binned) via multiplexers (MUXs). The outputs of the multiplexers (MUXs) are then sent, in sequence, to the PGA via a switch network. As the signal binning is performed in a column-wise manner, the binning technique shown in FIG. 2 is commonly referred to as a horizontal binning technique.
Accordingly, it is observed that the conventional readout architecture for an image sensor, for example, as shown in FIG. 1 requires a relatively large number of column amplifiers (CAs) and, thus, a relatively large chip area. As the number of columns increases, the number of CAs consequently increases, thereby occupying a substantial portion of the chip. It is also observed that, in the conventional readout architecture for an image sensor with binning function as shown in FIG. 2, the signal binning performed after the CAs disadvantageously affects the SNR.
For the reason that conventional readout architectures for the image sensor suffer a variety of disadvantages, a need has arisen to propose a novel readout architecture for an image sensor to improve the SNR and reduce chip area.